s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 173

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
LDD —
LDD
Operation:
Description:
Example:
In this example, assume that register pair HL contains 20H and internal RAM location 20H contains
the value 0FH:
LD
LDD
JPS
JPS
The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and instruction
'JPS YYY' is executed.
Load Data Memory and Decrement
dst
The contents of a data memory location are loaded into the accumulator, and the contents of the
register L are decremented by one. If a "borrow" occurs (e.g., if the resulting value in register L is
0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not
affected.
Operand
Operand
A,@HL
A,@HL
HL,#20H
A,@HL
XXX
YYY
Load indirect data memory contents to A; decrement
register L contents and skip on borrow
1
0
0
Binary Code
Operation Summary
0
; A
; Skip
; H
1
0
2H and L
(HL) and L
1
1
0FH
A
skip if L = 0FH
L–1
(HL), then L
Operation Notation
SAM47 INSTRUCTION SET
Bytes
1
L–1;
Cycles
2 + S
5-69