s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 72

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s3c72m9

Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
MEMORY MAP
IEW
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
.3–.2
IEW
IRQW
NOTE:
4-18
,
Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.
IRQW
— INTW Interrupt Enable/Request Flags
Bits 3–2
INTW Interrupt Enable Flag
INTW Interrupt Request Flag
0
0
1
R/W
"0"
1/4
3
0
Always logic zero
Disable INTW interrupt requests
Enable INTW interrupt requests
Generate INTW interrupt (This bit is set when the timer interval is set to 0.5
seconds or 3.91 milliseconds.)
R/W
"0"
1/4
2
0
R/W
IEW
1/4
1
0
IRQW
R/W
¼
0
0
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
CPU
FBAH

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