s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 239

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
I/O PORTS
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I/O PORTS
OVERVIEW
The S3C72M5/C72M7/C72M9 has 13 ports. There are total of 4 input pins and 47 configurable I/O pins, for a
maximum number of 51 pins.
Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read,
written, or tested at the corresponding address using bit manipulation instructions.
Port Mode Flags
Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding
I/O buffer.
Pull-up Resistor Mode Register (PUMOD)
The pull-up mode registers (PUMOD1, 2) are used to assign internal pull-up resistors by software to specific ports.
When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled,
even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
N-Channel Open-Drain Mode Register
The n-channel, open-drain mode register, PNE, is used to configure ports 0, 2, 3, 4, 6–13 to n-channel, open-drain
mode or as push-pull outputs.
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