s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 92

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

MEMORY MAP
PSW
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
C
SC2–SC0
IS1, IS0
EMB
ERB
NOTES:
1.
2.
4-38
The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during
power-down mode (IDLE or STOP), the current value of the carry flag is retained.
The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for
detailed information.
— Program Status Word
Carry Flag
Skip Condition Flags
Interrupt Status Flags
Enable Data Memory Bank Flag
Enable Register Bank Flag
0
1
0
1
0
0
1
1
0
1
0
1
R/W
(1)
(2)
C
7
No overflow or borrow condition exists
An overflow or borrow condition does exist
No skip condition exists; no direct manipulation of these bits is allowed
A skip condition exists; no direct manipulation of these bits is allowed
Restrict program access to data memory to bank 15 (F80H–FFFH) and to
the locations 000H–07FH in the bank 0 only
Enable full access to data memory banks 0–14, and 15
Select register bank 0 as working register area
Select register banks 0, 1, 2, or 3 as working register area in accordance with
the select register bank (SRB) instruction operand
0
1
0
1
Service all interrupt requests
Service only the high-priority interrupt(s) as determined in the interrupt
priority register (IPR)
Do not service any more interrupt requests
Undefined
SC2
R
6
0
8
SC1
R
5
0
8
SC0
R
4
0
8
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
R/W
IS1
1/4
3
0
CPU
R/W
IS0
1/4
2
0
EMB
R/W
1
0
1
FB1H, FB0H
ERB
R/W
0
0
1