s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 64
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 64 of 382
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MEMORY MAP
CLMOD2
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
CLMOD2.3
CLMOD2.2
CLMOD2.1
CLMOD2.0
NOTE:
4-10
If you set CLMOD1.3 and CLMOD2.0 flag to "1" simultaneously, the CLO1 and CLO2 clock output, 50% duty of
fxt (32.768 kHz), is enabled regardless of the values of CLMOD2.1 and CLMOD2.2.
— Clock Output Mode 2 Register
Clock duty selection Bit
Enable/Disable CLO2 Clock Output Control Bit
Enable/Disable CLO1 Clock Output Control Bit
Clock Source Selection Bits
0
1
0
1
0
1
0
1
W
.3
3
0
4
50 % duty
75 % duty
Disable CLO2 clock output
Enable CLO2 clock output
Disable CLO1 clock output
Enable CLO1 clock output
Decided by CLMOD1.1–.0
fxt (32.768 kHz) and 50 % duty only
W
.2
2
0
4
W
.1
1
0
4
W
.0
0
0
4
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
CPU
FD1H
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