s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 229

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
8
OVERVIEW
The S3C72M5/C72M7/C72M9 microcontroller has two power-down modes to reduce power consumption: idle and
stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP
instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while
peripherals and the oscillation source continue to operate normally.
When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed,
normal CPU operation resumes.
In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hardware
components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU, basic
timer, serial I/O, timer/ counters 0 and 1, watch timer, and LCD controller — and on external interrupt requests, is
detailed in Table 8-1.
Idle or stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding
interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is executed.
Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is
released immediately upon entering power-down mode.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt
master enable flag (IME):
— If the IME flag = "0", program execution starts immediately after the instruction which issues the request to
— If the IME flag = "1", two instructions are executed after the power-down mode release and the vectored interrupt
enter power-down mode is executed. The interrupt request flag remains set to logical one.
is then initiated. However, when the release signal is caused by INT2 or INTW, the operation is identical to the
IME = "0" condition. Assuming that both interrupt enable flag and interrupt request flag are set to "1", the
release signal is generated when power-down mode is entered.
Do not use stop mode if you are using an external clock source because X
internally to V
POWER-DOWN
SS
to reduce current leakage.
NOTE
IN
input must be restricted
POWER-DOWN
8-1