s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 2
![no-image](/images/no-image-200.jpg)
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 2 of 382
- Download datasheet (2Mb)
PRODUCT OVERVIEW
FEATURES SUMMARY
Memory
•
•
51 I/O Pins
•
•
LCD Controller/Driver
•
•
•
•
•
8-bit Basic Timer
•
•
8-bit Timer/Counter
•
•
•
•
1-2
3,584
(Excluding LCD Display
RAM)
16,384/24,576/32,768
8-bit ROM
I/O: 47 pins (32 pins are
configurable as SEG pins)
Input only: 4 pins
80 SEG
Internal resistor circuit for
LCD bias
16 Level LCD contrast
control (software)
Segment expandable circuit
All dot can be switched
on/off
4 interval timer functions
Watch-dog timer
Programmable 8-bit timer
External event counter
Arbitrary clock frequency
output
External clock signal divider
8 COM Terminals
4-bit RAM
16 COM, 88 SEG
16-Bit Timer/Counter
•
•
•
•
•
•
Watch Timer
•
•
•
8-bit Serial I/O Interface
•
•
•
•
Comparator
•
•
Interrupts
•
•
•
Programmable 16-bit timer
External event counter
Arbitrary clock frequency
output
External clock signal divider
Configurable as two 8-bit
Timers
Serial I/O interface clock
generator
Time interval generation: 0.5
s, 3.9 ms at 32,768 Hz
4 frequency outputs to BUZ
pin
Clock source generation for
LCD
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first
transmission selectable
Internal or external clock
source
3 Channel mode: internal
reference (4-bit resolution)
2 Channel mode: external
reference
Five internal vectored
interrupts
Four external vectored
interrupts
Two quasi-interrupts
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Bit Sequential Carrier
•
Memory-Mapped I/O Structure
•
Power-Down Modes
•
•
•
Oscillation Sources
•
•
•
•
•
Instruction Execution Times
•
•
•
Operating Temperature
•
Operating Voltage Range
•
Package Type
•
Supports 16-bit serial data
transfer in arbitrary format
Data memory bank 15
Idle mode (only CPU clock
stops)
Stop mode (main system
clock stops)
Subsystem clock stop mode
Crystal, Ceramic or RC for
main system clock
Crystal oscillator for
subsystem clock
Main system clock
frequency: 0.4–6 MHz
Subsystem clock frequency:
32.768 kHz
CPU clock divider circuit (by
4, 8 or 64)
0.67, 1.33, 10.7 µs at 6 MHz
0.95, 1.91, 15.3 µs at 4.19
MHz
122 µs at 32.768 kHz
– 40 C to 85 C
1.8 V to 5.5 V
128-pin QFP
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