s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 218

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

INTERRUPTS
Multi-Level Interrupt Handling
With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt is
being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7-2).
When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1" and
"0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority request is
accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be
serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4).
7-6
Process Status
0
1
2
–
INT Disable
INT Enable
High Level
Generated
Interrupt
Set IPR
Low or
Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling
Normal Program
IS1
Processing
(Status 0)
0
0
1
1
Before INT
IS0
0
1
0
1
Figure 7-4. Multi-Level Interrupt Handling
All interrupt requests are serviced.
Only high-priority interrupts as determined by the
current settings in the IPR register are serviced.
No additional interrupt requests will be serviced.
Value undefined
Modify Status
INT Disable
INT Enable
High Level
Generated
Interrupt
Low or
Effect of ISx Bit Setting
Interrupt
Single
Status 1
Status 0
Status 0
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
High Level
Generated
Interrupt
Interrupt
2-Level
Status 1
Interrupt
3-Level
Status 2
After INT ACK
IS1
0
1
–
–
IS0
1
0
–
–