s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 251

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Oscillation Stabilization Interval Control
Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also
determines the time interval (also referred to as ‘wait time’) required to stabilize clock signal oscillation when stop
mode is released by an interrupt. When a
clock oscillation following the
NOTE:
Register
WDMOD
WDTCF
BMOD
Name
BCNT
'U' means the value is undetermined after a RESET.
Counter
Control
Control
Control
Type
Controls the clock frequency
(mode) of the basic timer; also,
the oscillation stabilization
interval after stop mode release
or
Counts clock pulses matching
the BMOD frequency setting
Controls watchdog timer
operation.
Clears the watchdog timer’s
counter.
RESET
RESET
Table 11-1. Basic Timer Register Overview
Description
is 31.3 ms at 4.19 MHz.
RESET
signal is inputted, the standard stabilization interval for system
Size
4-bit
8-bit
8-bit
1-bit
F86H–F87H
F98H–F99H
Address
F9AH.3
F85H
RAM
4-bit write-only;
BMOD.3: 1-bit
writeable
8-bit read-only
8-bit write-only
1-, 4-bit write
Addressing
TIMERS and TIMER/COUNTERS
Mode
U
Value
Reset
A5H
(note)
“0”
“0”
11-3