s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 197
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 197 of 382
- Download datasheet (2Mb)
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
XCHD —
XCHD
Operation:
Description:
Example:
Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH:
YYY XCHD A,@HL
The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction.
dst,src
The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed
by register pair HL and then decrements the contents of register L. If the content of register L is
0FH, the next instruction is skipped. The value of the carry flag is not affected.
Exchange and Decrement
Operand
Operand
A,@HL
A,@HL
LD
LD
XCHD
JPS
JPS
•
•
•
Exchange A and data memory contents; decrement
contents of register L and skip on borrow
0
1
HL,#20H
A,#0H
A,@HL
XXX
YYY
1
Binary Code
Operation Summary
1
; A
; Skipped since a borrow occurred
; H
; (2FH)
1
0
2H, L
0FH and L
0FH, A
1
0FH
1
A
skip if L = 0FH
(2FH), L
L – 1, (HL)
(HL), then L
Operation Notation
L – 1 = 0EH
SAM47 INSTRUCTION SET
Bytes
"0"
1
L–1;
Cycles
2 + S
5-93
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