s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 32

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

ADDRESS SPACES
POP OPERATIONS
For each push operation there is a corresponding pop operation to write data from the stack back to the source
register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for
interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by
the type of operation and points to the next free stack location.
POP Instructions
A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and
SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After
the POP has executed, the SP is incremented by two and points to the next free stack location.
RET and SRET Instructions
The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to
reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the
ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location.
IRET Instructions
The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-bit
stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has
executed, the SP is incremented by six and points to the next free stack location.
2-16
SP + 1
SP + 2
SP
(SP
Lower Register
Upper Register
POP
SP + 2)
Figure 2-8. Pop-Type Stack Operations
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP
0
0
0
(SP
RET or SRET
PC11 - PC8
PC3 - PC0
PC7 - PC4
0
0
PC14 - PC12
PSW
SP + 6)
EMB ERB
0
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
0
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP
IS1
C
0
(SP
PC11 - PC8
SC2
PC3 - PC0
PC7 - PC4
IS0
PC14 - PC12
IRET
PSW
SP + 6)
EMB
SC1 SC0
ERB