s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 62
![no-image](/images/no-image-200.jpg)
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 62 of 382
- Download datasheet (2Mb)
MEMORY MAP
BMOD
Bit
Identifier
RESET Value
Read/Write
Bit Addressing
BMOD.3
BMOD.2–.0
NOTES:
1.
2.
3.
4-8
Interrupt interval time is the time required to set the IRQB to "1" periodically.
When a RESET occurs, the oscillation stabilization time is 31.3 ms (2
'fxx' is the system clock rate given a clock frequency of 4.19 MHz.
— Basic Timer Mode Register
Basic Timer Restart Bit
Input Clock Frequency and Signal Stabilization Interval Control Bits
1
0
0
1
1
1/4
W
.3
3
0
Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
0
1
0
1
0
1
1
1
W
.2
2
0
4
Input clock frequency:
Interrupt interval time:
Input clock frequency:
Interrupt interval time:
Input clock frequency:
Interrupt interval time:
Input clock frequency:
Interrupt interval time:
W
.1
1
0
4
W
.0
0
0
4
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
17
/fxx) at 4.19 MHz.
fxx/2
2
fxx/2
2
fxx/2
2
fxx/2
2
20
17
15
13
/fxx (250 ms)
/fxx (31.3 ms)
/
/fxx (1.95 ms)
fxx (7.82 ms)
BT
12
9
7
5
(131 kHz)
(8.18 kHz)
(32.7 kHz)
(1.02 kHz)
F85H
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