s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 259

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
TC0 COMPONENT SUMMARY
Mode register (TMOD0)
Reference register (TREF0)
Counter register (TCNT0)
Clock selector circuit
8-bit comparator
Output latch (TOL0)
Output enable flag (TOE0)
Interrupt request flag (IRQT0)
Interrupt enable flag (IET0)
Register
TMOD0
TREF0
TCNT0
Name
TOE0
Reference
Counter
Control
Type
Flag
Controls TC0 enable/disable (bit
2); clears and resumes counting
operation (bit 3); sets input
clock and clock frequency (bits
6–4)
Counts clock pulses matching
the TMOD0 frequency setting
Stores reference value for the
timer/counter 0 interval setting
Controls timer/counter 0 output
to the TCLO0 pin
Activates the timer/counter and selects the internal clock frequency or the
external clock source at the TCL0 pin.
Stores the reference value for the desired number of clock pulses between
interrupt requests.
Counts internal or external clock pulses based on the bit settings in TMOD0 and
TREF0.
Together with the mode register (TMOD0), lets you select one of four internal
clock frequencies or an external clock.
Determines when to generate an interrupt by comparing the current value of the
counter register (TCNT0) with the reference value previously programmed into the
reference register (TREF0).
Where a clock pulse is stored pending output to the TC0 output pin, TCLO0.
When the contents of the TCNT0 and TREF0 registers coincide, the
timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is in-
verted, and an interrupt is generated.
Must be set to logic one before the contents of the TOL0 latch can be output to
TCLO0.
Cleared when TC0 operation starts and the TC0 interrupt service routine is
executed and set to 1 whenever the counter value and reference value coincide.
Must be set to logic one before the interrupt requests generated by timer/counter
0 can be processed.
Table 11-4. TC0 Register Overview
Description
Size
8-bit
8-bit
8-bit
1-bit
F90H–F91H
F94H–F95H
F96H–F97H
Address
F92H.2
RAM
TIMERS and TIMER/COUNTERS
(TMOD0.3 is also
8-bit write-only;
1-bit writeable)
8-bit write-only
1-bit write-only
8-bit read-only
Addressing
Mode
Value
Reset
FFH
"0"
"0"
"0"
11-11