s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 272

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

TIMERS and TIMER/COUNTERS
TIMER/COUNTER 1 COMPONENT SUMMARY
Mode register (TMOD1A)
Reference register (TREF1)
Counter register (TCNT1)
Clock selector circuit
16-bit comparator
Output latch (TOL1)
Output enable flag (TOE1)
Interrupt request flag (IRQT1)
Interrupt enable flag (IET1)
11-24
Register
TMOD1A
TREF1
TCNT1
Name
TOE1
Reference
Counter
Control
Type
Flag
Controls TC1 enable/disable (bit
2); clears and resumes counting
operation (bit 3); sets input
clock and the clock frequency
(bits 6–4)
Select 16-bit TC1 or two 8-bit
TC1A and TC1B (bit 7)
Counts clock pulses matching
the TMOD1A frequency setting
Stores reference value for TC1
interval setting
Controls TC1 output to the
TCLO1 pin
Activates the timer/counter and selects the internal clock frequency or the
external clock source at the TCL1 pin.
Stores the reference value for the desired number of clock pulses between
interrupt requests.
Counts internal clock pulses that are generated based on bit settings in the
mode register and reference register.
Together with the mode register (TMOD1A), lets you select one of four internal
clock frequencies, or the external system clock source.
Determines when to generate an interrupt by comparing the current value of the
counter (TCNT1) with the reference value previously programmed into the
reference register (TREF1).
Where a TC1 clock pulse is stored pending output to the serial I/O circuit or to
the TC1 output pin, TCLO1. When the contents of the TCNT1 and TREF1
registers coincide, the timer/counter interrupt request flag (IRQT1) is set to "1",
the status of TOL1 is inverted, and an interrupt is generated.
Must be set to logic one before the contents of the TOL1 latch can be output to
TCLO1.
Cleared when TC1 operation starts and set to logic one whenever the counter
value and reference value match.
Must be set to logic one before the interrupt requests generated by timer/counter
1 can be processed.
Description
Table 11-8. TC1 Register Overview
16-bit
16-bit
Size
8-bit
1-bit
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
FA4H–FA5H,
FA8H–FA9H,
FAAH–FABH
FA0H–FA1H
FA6H–FA7H
Address
F92H.3
RAM
8-bit write-only;
8-bit write-only
1-bit write-only
(TMOD1A.3 is
(TMOD1A.7 is
8-bit read-only
Addressing
writeable)
also 1-bit
Mode
"1")
FFFFH
Value
Reset
"0"
"0"
"0"