s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 43

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
EMB AND ERB INITIALIZATION VALUES
The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector
address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB
flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table
is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the
interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has
completed.
At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by using
VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR) despite the
current SMB setting.
F
The following assembly instructions show how to initialize the EMB and ERB flag settings:
RESET
PROGRAMMING TIP — Initializing the EMB and ERB Flags
ORG
VENT0
VENT1
VENT2
VENT3
VENT4
VENT5
VENT6
VENT7
•
•
•
BITR
0000H
1,0,RESET
0,1,INTB
0,1,INT0
0,1,INT1
0,1,INTS
0,1,INTT0
0,1,INTT1
0,1,INTK
EMB
; ROM address assignment
; EMB
; EMB
; EMB
; EMB
; EMB
; EMB
; EMB
; EMB
0, ERB
1, ERB
0, ERB
0, ERB
0, ERB
0, ERB
0, ERB
0, ERB
1, branch INTB
1, branch INTT1
0, branch RESET
1, branch INT0
1, branch INT1
1, branch INTS
1, branch INTT0
1, branch INTK
ADDRESSING MODES
3-3