s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 292
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s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 292 of 382
- Download datasheet (2Mb)
TIMERS and TIMER/COUNTERS
TC1A COUNTER REGISTER (TCNT1A)
The 8-bit counter register for timer/counter 1A, TCNT1A, is mapped to RAM addresses FA5H–FA4H. The 8-bit
register is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1A register
values to logic zero (00H).
Whenever TMOD1A.2 and TMOD1A.3 are enabled, TCNT1A is cleared to logic zero and counting begins. The
TCNT1A register value is incremented each time an incoming clock signal is detected that matches the signal edge
and frequency setting of the TMOD1A register (specifically, TMOD1A.6, TMOD1A.5, and TMOD1A.4).
Each time TCNT1A is incremented, the new value is compared to the reference value stored in the TC1A reference
register, TREF1A. When TCNT1A = TREF1A, an overflow occurs in the TCNT1A register, the interrupt request flag,
IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval
has elapsed.
11-44
TCNT1A
TREF1A
Timer Start Instruction
Count
Clock
TOL1
(TMOD1A.3 is set)
0
1
2
Figure 11-7. TC1A Timing Diagram
n-1
IRQT1 Set
n
Reference Value = n
Match
0
1
Interval Time
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
2
n-1
IRQT1 Set
n
Match
0
1
2
3
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