s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 5
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s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 5 of 382
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S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also used
to restore a program's execution environment when an interrupt has been serviced. Program instructions can always
address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C
SC2
SC1
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the carry
flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be addressed
using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register banks:
the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, ….., or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a Crystal, Ceramic, or RC oscillation source, or an externally-generated
clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU clock,
and the clock used during power-down mode. The internal system clock signal (fxx) can be divided internally to
produce four CPU clock frequencies — fx/4, fx/8, fx/64, or fxt/4.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or externally by
peripheral devices (INT0, INT1, INT4, and INTK). There are two quasi-interrupts: INT2 and INTW.
INT2 detects rising or falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91
milliseconds. The following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-5
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