s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 236

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

RESET
HARDWARE RESET VALUES AFTER RESET
Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-down
mode or during normal operation.
NOTE:
9-2
Program counter (PC)
Carry flag (C)
Skip flag (SC0–SC2)
Interrupt status flags (IS0, IS1)
Bank enable flags (EMB, ERB)
General registers E, A, L, H, X, W, Z, Y
General purpose registers
Bank selection registers (SMB, SRB)
BSC register (BSC0–BSC3)
Power control register (PCON)
Clock output mode 1 register (CLMOD1)
Clock output mode 2 register (CLMOD2)
System clock mode register (SCMOD)
Interrupt request flags (IRQx)
Interrupt enable flags (IEx)
Interrupt priority flag (IPR)
Interrupt master enable flag (IME)
INT0 mode register (IMOD0)
INT1 mode register (IMOD1)
INT2 mode register (IMOD2)
INTK mode register (IMODK)
Program Status Word (PSW):
The values of the 0F8H–0FDH are not retained when a RESET signal is input.
Hardware Component
Data Memory (RAM):
or Subcomponent
Stack pointer (SP)
Interrupts:
Clocks:
Table 9-1. Hardware Register Values After RESET
Lower six bits of address 0000H
are transferred to PC13–8, and
the contents of 0001H to PC7–0.
Retained
Bit 6 of address 0000H in program
memory is transferred to the ERB
flag, and bit 7 of the address to
the EMB flag.
Values retained
Values retained
If RESET Occurs During
Power-Down Mode
Undefined
0, 0
(note)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Lower six bits of address 0000H
are transferred to PC13–8, and
the contents of 0001H to PC7–0.
Undefined
Bit 6 of address 0000H in program
memory is transferred to the ERB
flag, and bit 7 of the address to
the EMB flag.
Undefined
Undefined
If RESET Occurs During
Normal Operation
Undefined
0, 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0