s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 265

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
TC0 MODE REGISTER (TMOD0)
TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit,
TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0,
and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0
operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are retained
until TC0 is re-enabled.
The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This selection
involves two variables:
— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input
— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal
F90H
F91H
Bit Name
TMOD0.7
TMOD0.6
TMOD0.5
TMOD0.4
TMOD0.3
TMOD0.2
TMOD0.1
TMOD0.0
at the TCL0 pin, and
TC0 operation.
TMOD0.3
"0"
Setting
0,1
0
1
0
1
0
0
TMOD0.2
TMOD0.6
Table 11-6. TC0 Mode Register (TMOD0) Organization
Always logic zero
Specify input clock edge and internal frequency
Clear TCNT0, IRQT0, and TOL0 and resume counting immedi-
ately (This bit is automatically cleared to logic zero immediately
after counting resumes.)
Disable timer/counter 0; retain TCNT0 contents
Enable timer/counter 0
Always logic zero
Always logic zero
TMOD0.5
"0"
Resulting TC0 Function
TMOD0.4
"0"
TIMERS and TIMER/COUNTERS
Address
F91H
F90H
11-17