s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 339

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
SERIAL I/O MODE REGISTER (SMOD)
The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface. Its
reset value is logical zero. SMOD is organized in two 4-bit registers, as follows:
SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in
transmit-and-receive mode or receive-only mode. SMOD is a write-only register and can be addressed only by 8-bit
RAM control instructions. One exception to this is SMOD.3, which can be written by a 1-bit RAM control instruction.
When SMOD.3 is set to 1, the contents of the serial interface interrupt request flag, IRQS, and the 3-bit serial clock
counter are cleared, and SIO operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to
logical zero.
NOTES:
1.
2.
3.
4. When using the external clock as the SCK clock, the P0.0 must be set as an input pin. When using the
5. When using SI and SO as data input/output pins, they must each be set as input/output pins.
6. It must be selected MSB-first or LSB-first transmission mode before loading a data to SBUF.
SMOD.0
SMOD.1
SMOD.2
SMOD.3
SMOD.4
SMOD.7
FE0H
FE1H
'fxx' = system clock; 'x' means 'don't care'.
kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz.
The SIO clock selector circuit cannot select a fxx/2
internal clock as the SCK clock, the P0.0 must be set as an output pin.
0
0
0
1
1
SMOD.3
SMOD.7
SMOD.6
0
1
0
1
0
1
1
0
0
0
1
0
1
Most significant bit (MSB) is transmitted first
Least significant bit (LSB) is transmitted first
Receive-only mode
Transmit-and-receive mode
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset this
bit to logic zero
Bit not used; value is always "0"
SMOD.2
SMOD.6
Table 13-1. SIO Mode Register (SMOD) Organization
SMOD.5
0
1
x
0
1
External clock at SCK pin
Use TOL1 clock from TC1
CPU clock: fxx/4, fxx/8, fxx/64
4.09 kHz clock: fxx/2
262 kHz clock: fxx/2
SMOD.1
SMOD.5
4
Clock Selection
clock if the CPU clock is fxx/64
SMOD.0
0
4
10
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
Enable SBUF read/write
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
.
R/W Status of SBUF
SERIAL I/O INTERFACE
13-3