s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 226

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

INTERRUPTS
Interrupt Request Flags (IRQx)
Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly
at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.
When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then
automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt
request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt
service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary,
follow these guidelines for using IRQx flags:
1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.
2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the
3. When IRQx is set to "1" by software, an interrupt is generated.
When two interrupts share the same service routine start address, interrupt processing may occur in one of two
ways:
— When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been serviced.
— When two interrupts are enabled, the request flag is not automatically cleared so that the user has an
7-14
Interrupt
(INTT1A)
exception of IRQW and IRQ2).
opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared manually
using a BTSTZ instruction.
Source
INTT1B
INTT0
INTT1
INTW
INTB
INTS
INTK
INT4
INT0
INT1
INT2
Internal /
External
E
E
E
E
E
I
I
I
I
I
I
Table 7-8. Interrupt Request Flag Conditions and Priorities
Reference time interval signal from basic timer
Both rising and falling edges detected at INT4
Rising or falling edge detected at INT0 pin
Rising or falling edge detected at INT1 pin
Completion signal for serial transmit-and-receive
or receive-only operation
Signals for TCNT0 and TREF0 registers match
Signals for TCNT1B and TREF1B registers
match
Signals for TCNT1(TCNT1A) and TREF1
(TREF1A) registers match
When a rising or falling edge detected at any
one of the K0–K7 pins
Rising or falling edge detected at INT2
Time interval of 0.5 secs or 3.19 msecs
Pre-condition for IRQx Flag Setting
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
Interrupt
Priority
1
1
2
3
4
5
5
6
7
–
–
IRQ Flag
Name
IRQT0
IRQT2
IRQT1
IRQW
IRQB
IRQS
IRQK
IRQ4
IRQ0
IRQ1
IRQ2