s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 289
![no-image](/images/no-image-200.jpg)
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 289 of 382
- Download datasheet (2Mb)
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
TC1A SERIAL I/O CLOCK GENERATION
Timer/counter1A can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and
clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD).
This clock generation function enables you to adjust data transmission rates across the serial interface.
Use TMOD1A and TREF1A, TREF1B register settings to select the frequency and interval of the TC1A clock signals
to be used as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O
clock selector circuit (the TOE1 flag may be disabled).
TC1A EXTERNAL INPUT SIGNAL DIVIDER
By selecting an external clock source and loading a reference value into the TC1A reference register, TREF1A, you
can divide the incoming clock signal by the TREF1A value and then output this modified clock frequency to the
TCLO1 pin. The sequence of operations used to divide external clock input and output the signals to the TCLO1 pin
can be summarized as follows:
1. Set TMOD1A.7 to "0" be operated as timer/counter 1A.
2. Load a signal divider value to the TREF1A register.
3. Clear TMOD1A.6 to "0" to enable external clock input at the TCLO1 pin.
4. Set TMOD1A.5 and TMOD1A.4 to desired TCL1 signal edge detection.
5. Set P3.1 mode flag (PM3.1) to output ("1").
6. Clear the P3.1 output latch.
7. Set TOE1 flag to "1" to enable output of the divided frequency.
F
Output the external TCL1 clock source to the TCLO1 pin (divide by four):
PROGRAMMING TIP — External TCL1 Clock Output to the TCLO1 Pin
External (TCL1)
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
Output Pulse
Clock Pulse
TCLO1
EMB
15
EA,#01H
TREF1A,EA
EA,#0CH
TMOD1A,EA
EA,#02H
PMG2,EA
P3.1
TOE1
; P3.1
; P3.1 clear
output mode
TIMERS and TIMER/COUNTERS
11-41
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