C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 101

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
typically less than 0.3 ms. Figure 11.2. plots the power-on and V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
RST
. A Power-On Reset delay (T
Logic HIGH
Logic LOW
2.70
2.4
2.0
1.0
Figure 11.2. Power-On and V
RST
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
V
RST
PORDelay
Power-On
Reset
) occurs before the device is released from reset; this delay is
T
PORDelay
Rev. 1.3
DD
Monitor Reset Timing
DD
Monitor
Reset
VDD
monitor reset timing.
DD
monitor is enabled following a
VDD
t
DD
settles above
101