C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 186

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
186
USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte
Bit7:
Bit6:
Bits5–0: Unused. Read = 000000b; Write = don’t care.
Bits7–0: EOCL: OUT Endpoint Count Low Byte
Bits7–2: Unused. Read = 00000. Write = don’t care.
Bits1–0: EOCH: OUT Endpoint Count High Byte
DBOEN
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low
R/W
Bit7
Bit7
Bit7
R
R
-
DBOEN: Double-buffer Enable
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
ISO: Isochronous Transfer Enable
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
ISO
R/W
Bit6
Bit6
Bit6
R
R
-
R/W
Bit5
Bit5
Bit5
R
R
-
-
R/W
Bit4
Bit4
Bit4
R
R
-
-
EOCL
Rev. 1.3
Bit3
Bit3
Bit3
R
R
R
-
-
Bit2
Bit2
Bit2
R
R
R
-
-
Bit1
Bit1
Bit1
R
R
R
-
E0CH
Bit0
Bit0
Bit0
R
R
R
-
USB Address:
USB Address:
USB Address:
00000000
00000000
00000000
Reset Value
Reset Value
Reset Value
0x15
0x17
0x16