C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 239

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when INT1 is active as
defined by bit IN1PL in register INT01CF (see SFR Definition 9.13).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive. INT1 is
configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
9.13).
0: INT1 is level triggered.
1: INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when INT0 is active as
defined by bit IN0PL in register INT01CF (see SFR Definition 9.13).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 9.13).
0: INT0 is level triggered.
1: INT0 is edge triggered.
TR1
R/W
Bit6
SFR Definition 21.1. TCON: Timer Control
TF0
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
TR0
R/W
Bit4
Rev. 1.3
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
(bit addressable)
R/W
IT0
Bit0
SFR Address:
00000000
Reset Value
0x88
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