C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 105

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a
read), read-modify-write instructions read and modify the source enable only. This applies to
bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF.
USBRSF FERROR C0RSEF
R/W
Bit7
USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On / V
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized can cause a system reset. See register VDM0CN (SFR Definition 11.1).
0: Read: Last reset was not a power-on or V
reset source.
1: Read: Last reset was a power-on or V
Write: V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Bit6
R
DD
monitor is a reset source.
SFR Definition 11.2. RSTSRC: Reset Source
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
DD
SWRSF
Monitor Reset Flag.
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.3
Bit3
DD
R
monitor reset; all other reset flags indeterminate;
DD
monitor reset; Write: V
R/W
Bit2
PORSF
R/W
Bit1
DD
PINRSF
DD
monitor is enabled
Bit0
R
monitor is not a
SFR Address:
Reset Value
Variable
0xEF
DD
105