C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 9

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

12. Flash Memory
13. External Data Memory Interface and On-Chip XRAM
14. Oscillators
15. Port Input/Output
16. Universal Serial Bus Controller (USB0)
17. SMBus
18. UART0
19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
Figure 12.1. Flash Program Memory Map and Security Byte................................. 110
Figure 13.1. USB FIFO Space and XRAM Memory Map 
Figure 13.2. Multiplexed Configuration Example.................................................... 119
Figure 13.3. Non-multiplexed Configuration Example ............................................ 120
Figure 13.4. EMIF Operating Modes ...................................................................... 120
Figure 13.5. Non-multiplexed 16-bit MOVX Timing ................................................ 124
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 125
Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 126
Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 127
Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 128
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 129
Figure 14.1. Oscillator Diagram.............................................................................. 131
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ................ 142
Figure 15.2. Port I/O Cell Block Diagram ............................................................... 143
Figure 15.3. Peripheral Availability on Port I/O Pins............................................... 144
Figure 15.4. Crossbar Priority Decoder in Example Configuration
Figure 15.5. Crossbar Priority Decoder in 
Figure 16.1. USB0 Block Diagram.......................................................................... 159
Figure 16.2. USB0 Register Access Scheme......................................................... 162
Figure 16.3. USB FIFO Allocation .......................................................................... 167
Figure 17.1. SMBus Block Diagram ....................................................................... 188
Figure 17.2. Typical SMBus Configuration ............................................................. 189
Figure 17.3. SMBus Transaction ............................................................................ 190
Figure 17.4. Typical SMBus SCL Generation......................................................... 193
Figure 17.5. Typical Master Transmitter Sequence................................................ 199
Figure 17.6. Typical Master Receiver Sequence.................................................... 200
Figure 17.7. Typical Slave Receiver Sequence...................................................... 201
Figure 17.8. Typical Slave Transmitter Sequence.................................................. 202
Figure 18.1. UART0 Block Diagram ....................................................................... 205
Figure 18.2. UART0 Baud Rate Logic .................................................................... 206
Figure 18.3. UART Interconnect Diagram .............................................................. 207
Figure 18.4. 8-Bit UART Timing Diagram............................................................... 207
Figure 18.5. 9-Bit UART Timing Diagram............................................................... 208
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram .......................... 209
with USBFAE set to ‘1’ ...................................................................................... 115
(No Pins Skipped) ............................................................................................. 145
Example Configuration (3 Pins Skipped) .......................................................... 146
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Rev. 1.3
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