C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 246

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
246
External Clock / 8
SYSCLK / 12
T
F
H
2
T
F
2
L
TMR2CN
E
N
T
F
2
L
C
E
T
2
T
2
S
P
L
T
I
R
T
2
T
2
C
S
S
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’)
T
X
C
K
2
L
0
1
SYSCLK
0
1
1
0
M
H
T
3
M
T
3
L
CKCON
M
H
T
2
M
T
2
L
M
T
1
M
T
0
TR2
S
C
A
1
S
C
A
0
Rev. 1.3
USB Start-of-Frame (SOF)
Low-Frequency Oscillator
TCLK
TCLK
Falling Edge
TMR2RLH
TMR2RLL
TMR2H
TMR2L
Capture
Capture
To SMBus
To ADC,
SMBus
T2CSS
0
1
Enable
Interrupt

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