C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 155

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bits7–0: P3.[7:0]
Note: P3.1–3.7 are only available on 48-pin devices.
Bits7–0: Analog Input Configuration Bits for P3.7–P3.0 (respectively).
Note: P3.1–3.7 are only available on 48-pin devices.
Bits7–0: Output Configuration Bits for P3.7–P3.0 (respectively); ignored if corresponding bit in regis-
Note: P3.1–3.7 are only available on 48-pin devices.
P3.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port
pin when configured as digital input.
0: P3.n pin is logic low.
1: P3.n pin is logic high.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P3.n pin is configured as an analog input.
1: Corresponding P3.n pin is not configured as an analog input.
ter P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
P3.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 15.18. P3MDOUT: Port3 Output Mode
SFR Definition 15.17. P3MDIN: Port3 Input Mode
P3.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 15.16. P3: Port3 Latch
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
P3.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.3
P3.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
P3.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
P3.1
R/W
R/W
R/W
Bit1
Bit1
Bit1
(bit addressable)
P3.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
Reset Value
Reset Value
Reset Value
11111111
11111111
0xB0
0xF4
0xA7
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