C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 210

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
210
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
S0MODE
R/W
Bit7
S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S0MODE = 0: Checks for valid stop bit.
S0MODE = 1: Multiprocessor Communications Enable.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in
8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the
UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt
service routine. This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART0 interrupt service routine. This bit must be cleared manually by soft-
ware.
Bit6
R
-
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
SFR Definition 18.1. SCON0: Serial Port 0 Control
MCE0
R/W
Bit5
REN0
R/W
Bit4
Rev. 1.3
TB80
R/W
Bit3
RB80
R/W
Bit2
R/W
TI0
Bit1
SFR Address:
R/W
RI0
Bit0
0x98
01000000
Addressable
Reset Value
Bit