C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 146

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
146
Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
S F Signa ls
(32-pin
P a cka ge )
S F Signa ls
(48-pin
P a cka ge )
P IN I/O
TX 0
RX0
S CK
M ISO
M OSI
NSS*
S DA
S CL
CP0
CP0A
CP1
CP1A
S YSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX 1**
RX1**
S F Signa ls
Port pin assigned to peripheral by the Crossbar
Special Function Signals are not assigned by the Crossbar. W hen these signals are
enabled, the Crossbar must be manually configured to skip their corresponding port pins.
0
0
1
0
2
1
P 0SKIP[0:7]
3
1
P 0
4
0
5
0
6
0
7
0
0
1
*NSS is only pinned out in 4-wire S PI m ode
1
0
2
0
P1S KIP[0:7]
3
0
P1
4
0
Rev. 1.3
5
0
6
0
7
0
0
0
**UA RT1 available only on C8051F340/1/4/5/8/A /B devices
1
0
2
0
P2SKIP[0:7]
3
0
P2
4
0
5
0
6
0
7
0
Example:
0
0
1
0
P3.1-P3.7 una va ila ble on
the 32-pin pa cka ge s
2
0
P3SKIP [0:7]
XBR0 = 0x07
XBR1 = 0x43
P 0SK IP = 0x0C
P 1SK IP = 0x01
3
0
P3
4
0
5
0
6
0
7
0