C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 236

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“15.1. Priority Crossbar Decoder” on page 144
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 21.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register INT01CF (see SFR Definition 9.13). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal INT0 (see
Descriptions” on page 90
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register INT01CF (see
SFR Definition 9.13).
21.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
236
INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
TR0
GATE0
), facilitating pulse width measurements.
0
1
1
1
X = Don't Care
Figure 21.1. T0 Mode 0 Block Diagram
XOR
TR0
0
1
GATE0
M
H
T
3
M
T
3
L
CKCON
X
M
H
0
1
1
T
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 1.3
for information on selecting and configuring external I/O
G
A
T
E
1
C
T
1
/
INT0
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
1
P
L
I
Counter/Timer
N
S
1
L
2
I
INT01CF
N
S
1
L
1
I
Disabled
Disabled
Enabled
Enabled
N
1
S
L
0
Section “9.3.5. Interrupt Register
I
N
P
0
L
(8 bits)
I
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Section