C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 245

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
21.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge
When T2CE = ‘1’, Timer 2 will operate in one of two special capture modes. The capture event can be
selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling
Edge capture, using the T2CSS bit. The USB SOF capture mode can be used to calibrate the system clock
or external oscillator against the known USB host SOF clock. The LFO falling-edge capture mode can be
used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or
an external clock source. When T2SPLIT = ‘0’, Timer 2 counts up and overflows from 0xFFFF to 0x0000.
Each time a capture event is received, the contents of the Timer 2 registers (TMR2H:TMR2L) are latched
into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled.
External Clock / 8
SYSCLK / 12
SYSCLK
T
F
H
2
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’)
T
F
2
L
USB Start-of-Frame (SOF)
Low-Frequency Oscillator
TMR2CN
N
T
F
2
L
E
C
E
T
2
S
P
T
2
L
T
I
Falling Edge
T
R
2
T
C
S
S
2
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
C
T
2
X
L
K
0
1
T
M
H
3
M
T
3
L
CKCON
M
T
H
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
T2CSS
TR2
Rev. 1.3
0
1
Enable
Capture
TCLK
Overflow
TL2
TMR2RLL TMR2RLH
TMR2L
Interrupt
To SMBus
TMR2H
To ADC,
SMBus
245

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