C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 165

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bits3–0: EPSEL: Endpoint Select
USB Register
EOUTCSRH
EOUTCNTH
EOUTCSRL
EOUTCNTL
EINCSRH
OUT1INT
FRAMEH
EINCSRL
FRAMEL
CLKREC
POWER
OUT1IE
Bit7
FADDR
E0CSR
E0CNT
IN1INT
CMINT
INDEX
FIFOn
Name
R
IN1IE
CMIE
-
These bits select which endpoint is targeted when indexed USB0 registers are accessed.
USB Register Definition 16.4. INDEX: USB0 Endpoint Index
Bit6
0x4–0xF
R
-
INDEX
0x0
0x1
0x2
0x3
USB Register
0x20–0x23
Address
0x0C
0x0D
0x06
0x09
0x0B
0x00
0x0E
0x0F
0x14
0x15
0x16
0x02
0x04
0x07
0x01
0x11
0x12
0x17
Table 16.2. USB0 Controller Registers
Bit5
R
-
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Target Endpoint
Endpoint0 and Endpoints1-3 IN Interrupt Flags
Endpoints1-3 OUT Interrupt Flags
Common USB Interrupt Flags
Endpoint0 and Endpoints1-3 IN Interrupt Enables
Endpoints1-3 OUT Interrupt Enables
Common USB Interrupt Enables
Function Address
Power Management
Frame Number Low Byte
Frame Number High Byte
Endpoint Index Selection
Clock Recovery Control
Endpoints0-3 FIFOs
Endpoint0 Control / Status
Endpoint IN Control / Status Low Byte
Endpoint IN Control / Status High Byte
Endpoint OUT Control / Status Low Byte
Endpoint OUT Control / Status High Byte
Number of Received Bytes in Endpoint0 FIFO
Endpoint OUT Packet Count Low Byte
Endpoint OUT Packet Count High Byte
Reserved
Bit4
R
-
Common Registers
Interrupt Registers
Indexed Registers
0
1
2
3
Rev. 1.3
R/W
Bit3
Description
R/W
Bit2
EPSEL
R/W
Bit1
R/W
Bit0
Page Number
USB Address:
00000000
Reset Value
176
166
173
173
174
175
175
169
171
172
172
165
168
179
182
183
185
186
180
186
186
0x0E
165