C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 113

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Bits7:
Bits6–5: RESERVED. Read = 00b. Must Write 00b.
Bit 4:
Bits3–0: RESERVED. Read = 0000b. Must Write 0000b.
FOSE
R/W
Bit7
FOSE: Flash One-shot Enable
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash
sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen-
cies below 10 MHz, disabling the Flash one-shot will increase system power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
FLRT: FLASH Read Time.
This bit should be programmed to the smallest allowed value, according to the system clock
speed.
0: SYSCLK <= 25 MHz.
1: SYSCLK <= 48 MHz.
Reserved Reserved
R/W
Bit6
SFR Definition 12.3. FLSCL: Flash Scale
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
FLRT
R/W
Bit4
Reserved Reserved Reserved Reserved 10000000
Rev. 1.3
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
0xB6
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