C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 213

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in
FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.
UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and
SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is
used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit
holding register and the receive FIFO. Writes to SBUF1 always access the Transmit Holding Register.
Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data
from the Transmit Holding Register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by
software.
SYSCLK
SBRLH1
Timer (16-bit)
Baud Rate Generator
SBRLL1
EN
SBCON1
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Overflow
Figure 19.1. UART1 Block Diagram
Section “19.1. Baud Rate Generator” on page 214
(1, 4, 12, 48)
Pre-Scaler
Rev. 1.3
Data Formatting
Control / Status
Interrupt
UART1
SMOD1
SCON1
TX Holding
RX FIFO
(3 Deep)
Register
SBUF1
Logic
Logic
RX
TX
). A received data
Write to SBUF1
Read of SBUF1
TX1
RX1
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