C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 215

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

19.2. Data Format
UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor com-
munication mode is available for implementing networked UART buses. All of the data formatting options
can be configured using the SMOD1 register, shown in SFR Definition 19.2. Figure 19.2 shows the timing
for a UART1 transaction without parity or an extra bit enabled. Figure 19.3 shows the timing for a UART1
transaction with parity enabled (PE1 = 1). Figure 19.4 is an example of a UART1 transaction when the
extra bit is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled, and
the second stop bit is only an option for data lengths of 6, 7, or 8 bits.
SPACE
SPACE
MARK
MARK
BIT TIMES
BIT TIMES
SPACE
MARK
BIT TIMES
START
START
BIT
BIT
Figure 19.2. UART1 Timing Without Parity or Extra Bit
START
BIT
D
D
Figure 19.4. UART1 Timing With Extra Bit
0
0
Figure 19.3. UART1 Timing With Parity
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
D
0
D
D
1
1
N bits; N = 5, 6, 7, or 8
N bits; N = 5, 6, 7, or 8
D
1
N bits; N = 5, 6, 7, or 8
Rev. 1.3
D
D
N-2
N-2
D
N-2
D
D
N-1
N-1
D
N-1
PARITY
EXTRA
STOP
BIT 1
STOP
STOP
BIT 1
BIT 1
Optional
STOP
BIT 2
Optional
Optional
STOP
STOP
BIT 2
BIT 2
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