C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 219

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Bit7:
Bits6–5: S1PT[1:0]: Parity Type.
Bit4:
Bits3–2: S1DL[1:0]: Data Length.
Bit1:
Bit0:
MCE1
R/W
Bit7
MCE1: Multiprocessor Communication Enable.
0: RI will be activated if stop bit(s) are ‘1’.
1: RI will be activated if stop bit(s) and extra bit are ‘1’ (extra bit must be enabled using
XBE1).
Note: This function is not available when hardware parity is enabled.
00: Odd
01: Even
10: Mark
11: Space
PE1: Parity Enable.
This bit activates hardware parity generation and checking. The parity type is selected by
bits S1PT1-0 when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
XBE1: Extra Bit Enable
When enabled, the value of TBX1 will be appended to the data field.
0: Extra Bit Disabled.
1: Extra Bit Enabled.
SBL1: Stop Bit Length
0: Short - Stop bit is active for one bit time.
1: Long - Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
S1PT1
R/W
Bit6
SFR Definition 19.2. SMOD1: UART1 Mode
S1PT0
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
PE1
R/W
Bit4
Rev. 1.3
S1DL1
R/W
Bit3
S1DL0
R/W
Bit2
XBE1
R/W
Bit1
SFR Address:
SBL1
R/W
Bit0
0xE5
00001100
Reset Value
219

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