C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 60

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See
page 144
externally driven from –0.25 V to (V
trical specifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition
7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current. See
Table 7.1 for complete timing and supply current specifications.
60
CMXnN2
CMXnN1
CMXnN0
CMXnP2
CMXnP1
CMXnP0
Port I/O connection options vary with
package (32-pin or 48-pin)
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
Figure 7.1. Comparator Functional Block Diagram
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
CPnOUT
CPnRIF
CPnFIF
CPnEN
DD
CPn +
CPn -
) + 0.25 V without damage or upset. The complete Comparator elec-
CPnMD1
CPnMD0
CPnRIE
CPnFIE
Rev. 1.3
+
-
VDD
GND
Section “15.1. Priority Crossbar Decoder” on
(SYNCHRONIZER)
D
SET
CLR
Reset Decision Tree
(Comprator 0 Only)
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CPn
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CPn
CPnA
CPn
CPn
CPnRIE
CPnFIE

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