C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 179

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SSUEND SOPRDY
R/W
Bit7
USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control
SSUEND: Serviced Setup End
Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event.
Hardware clears the SUEND bit when software writes ‘1’ to SSUEND.
Read: This bit always reads ‘0’.
SOPRDY: Serviced OPRDY
Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The
OPRDY bit will be cleared by a write of ‘1’ to SOPRDY.
Read: This bit always reads ‘0’.
SDSTL: Send Stall
Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition,
unexpected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL hand-
shake is transmitted.
SUEND: Setup End
Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has
written ‘1’ to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to SSU-
END.
DATAEND: Data End
Software should write ‘1’ to this bit:
1. When writing ‘1’ to INPRDY for the last outgoing data packet.
2. When writing ‘1’ to INPRDY for a zero-length data packet.
3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be
cleared by software.
INPRDY: IN Packet Ready
Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for
transmit. Hardware clears this bit and generates an interrupt under either of the following
conditions:
1. The packet is transmitted.
2. The packet is overwritten by an incoming SETUP packet.
3. The packet is overwritten by an incoming OUT packet.
OPRDY: OUT Packet Ready
Hardware sets this read-only bit and generates an interrupt when a data packet has been
received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit.
R/W
Bit6
SDSTL
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SUEND DATAEND
Bit4
R
Rev. 1.3
R/W
Bit3
STSTL
R/W
Bit2
INPRDY
R/W
Bit1
OPRDY
Bit0
R
USB Address:
00000000
Reset Value
0x11
179