C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 115

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

13.2. Accessing USB FIFO Space
The C8051F34x devices include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an
expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO regis-
ters; see
FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to '1', and (2) the USB clock must be greater than or equal to
twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped into
XRAM space at addresses 0x0400 to 0x07FF. The normal XRAM (on-chip or external) at the same
addresses cannot be accessed when the USBFAE bit is set to ‘1’.
Important Note: The USB clock must be active when accessing FIFO space.
Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’
Section “16.5. FIFO Management” on page 167
0xFFFF
0x07FF
0x07C0
0x07BF
0x03FF
0x073F
0x063F
0x043F
0x0800
0x0740
0x0640
0x0440
0x0400
0x0000
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
On/Off-Chip XRAM
On/Off-Chip XRAM
(128 bytes)
(256 bytes)
(512 bytes)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Free
Rev. 1.3
USB FIFO Space
(USB Clock Domain)
for more information on accessing these
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