C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 40

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C8051F34A-GMR

Manufacturer Part Number
C8051F34A-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F34A-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
40
Notes:
General:
Solder Mask Design:
Stencil Design:
Card Assembly:
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60m minimum, all the way around the pad.
to assure good solder paste release.
the proper paste volume.
Body Components.
Figure 4.9. QFN-32 Recommended PCB Land Pattern
Table 4.7. QFN-32 PCB Land Pattern Dimesions
4.80
4.80
0.20
Min
0.50 BSC
Max
4.90
4.90
0.30
Rev. 1.3
Dimension
X2
Y1
Y2
3.20
0.75
3.20
Min
Max
3.40
0.85
3.40

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