C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 50

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
50
Bits7–0: ADC0 Data Word High-Order Bits.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bit2:
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
Bits7–0: ADC0 Data Word Low-Order Bits.
AD0SC4
R/W
R/W
R/W
Bit7
Bit7
Bit7
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
AD0SC
AD0SC3
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
SFR Definition 5.3. ADC0CF: ADC0 Configuration
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
=
SYSCLK
--------------------- - 1
CLK
AD0SC2
R/W
R/W
Bit5
R/W
Bit5
Bit5
SAR
–
AD0SC1
R/W
R/W
Bit4
R/W
Bit4
Bit4
AD0SC0 AD0LJST
Rev. 1.3
R/W
R/W
Bit3
R/W
Bit3
Bit3
R/W
R/W
Bit2
R/W
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
-
R/W
R/W
R/W
Bit0
Bit0
Bit0
-
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
Reset Value
11111000
0xBE
0xBC
0xBD