C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 102

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
11.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any
other reset source. For example, if the V
monitor will still be enabled after the reset. It is strongly recommended that the V
at all times for any system that contains code to write to Flash memory.
Important Note: The V
V
tions where this reset is undesirable, a delay can be implemented between enabling the V
selecting it as a reset source. The procedure for configuring the V
below:
See Figure 11.2 for V
monitor.
102
DD
Bit7:
Bit6:
Bits5–0: Reserved. Read = Variable. Write = don’t care.
VDMEN
monitor as a reset source before it is enabled and stabilized may cause a system reset. In applica-
R/W
Bit7
Step 1. Enable the V
Step 2. If desired, wait for the V
Step 3. Select the V
VDMEN: V
This bit turns the V
until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 11.1 for the minimum V
lowing all POR resets.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
DD
DD
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
DD
DD
DD
DD
time).
STAT: V
monitor as a reset source before it has stabilized will generate a system reset.
Bit6
RST
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
SFR Definition 11.1. VDM0CN: V
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
DD
DD
monitor timing. See Table 11.1 for complete electrical characteristics of the V
Monitor Enable.
monitor must be enabled before it is selected as a reset source. Selecting the
Status.
DD
Bit5
DD
R
DD
monitor as a reset source (RSTSRC.1 = ‘1’).
monitor (VDM0CN.7 = ‘1’).
DD
monitor circuit on/off. The V
DD
monitor threshold.
Monitor
DD
DD
Bit4
DD
R
monitor threshold.
monitor to stabilize (see Table 11.1 for the V
monitor is enabled and a software reset is performed, the V
DD
Rev. 1.3
Monitor turn-on time. The V
Bit3
R
DD
DD
Bit2
DD
R
DD
Monitor cannot generate system resets
Monitor Control
to drop below V
DD
Monitor output).
monitor as a reset source is shown
Bit1
R
DD
DD
Monitor is enabled fol-
monitor be left enabled
RST
Bit0
R
, the power supply
DD
DD
Monitor turn-on
DD
dropped below
SFR Address:
Reset Value
monitor and
Variable
DD
0xFF
returns
DD
DD
DD
DD