C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 203

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

1000
1110
1100
Values Read
0
0
0
1
0
0
0
0
X A master START was generated.
X
0
1
A master data or address byte
was transmitted; NACK received.
A master data or address byte
was transmitted; ACK received.
A master data byte was received;
ACK requested.
Table 17.4. SMBus Status Decoding
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Current SMbus State
Rev. 1.3
Load slave address + R/W
into SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and
start another transfer.
Send repeated START.
Switch to Master Receiver
Mode (clear SI without writ-
ing new data to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last
byte, and send STOP.
Send NACK to indicate last
byte, and send STOP fol-
lowed by START.
Send ACK followed by
repeated START.
Send NACK to indicate last
byte, and send repeated
START.
Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
Typical Response Options
0
1
0
0
1
0
1
1
1
0
1
0
0
0
0
Written
Values
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
X
X
203
1
0
0
1
0
1
0