C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 253

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF3H
R/W
Bit7
TF3H: Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine.
TF3H is not automatically cleared by hardware and must be cleared by software.
TF3L: Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L
will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automat-
ically cleared by hardware.
TF3LEN: Timer 3 Low Byte Interrupt Enable.
This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 inter-
rupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
This bit should be cleared when operating Timer 3 in 16-bit mode.
0: Timer 3 Low Byte interrupts disabled.
1: Timer 3 Low Byte interrupts enabled.
T3CE: Timer 3 Capture Enable
0: Capture function disabled.
1: Capture function enabled. The timer is in capture mode, with the capture event selected
by bit T3CSS. Each time a capture event is received, the contents of the Timer 3 registers
(TMR3H and TMR3L) are latched into the Timer 3 reload registers (TMR3RLH and
TMR3RLH), and a Timer 3 interrupt is generated (if enabled).
T3SPLIT: Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only;
TMR3L is always enabled in this mode.
0: Timer 3 disabled.
1: Timer 3 enabled.
T3CSS: Timer 3 Capture Source Select.
This bit selects the source of a capture event when bit T3CE is set to ‘1’.
0: Capture source is USB SOF event.
1: Capture source is rising edge of Low-Frequency Oscillator.
T3XCLK: Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 3 external clock selection is the system clock divided by 12.
1: Timer 3 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
TF3L
R/W
Bit6
SFR Definition 21.13. TMR3CN: Timer 3 Control
TF3LEN
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
T3CE
R/W
Bit4
T3SPLIT
Rev. 1.3
R/W
Bit3
TR3
R/W
Bit2
T3CSS
R/W
Bit1
T3XCLK 00000000
R/W
Bit0
SFR Address:
Reset Value
0x91
253