C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 204

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
204
0100
0101
0010
0010
0001
0000
Values Read
0
0
0
0
1
1
0
1
0
0
1
1
X
0
0
1
0
1
1
1
0
1
0
1
Table 17.4. SMBus Status Decoding (Continued)
X
X
X
X
X
X
X
X
X
X
0
1
A slave byte was transmitted;
NACK received.
A slave byte was transmitted;
ACK received.
A Slave byte was transmitted;
error detected.
An illegal STOP or bus error was
detected while a Slave Transmis-
sion was in progress.
A slave address was received;
ACK requested.
Lost arbitration as master; slave
address received; ACK
requested.
Lost arbitration while attempting a
repeated START.
Lost arbitration while attempting a
STOP.
A STOP was detected while
addressed as a Slave Transmitter
or Slave Receiver.
Lost arbitration due to a detected
STOP.
A slave byte was received; ACK
requested.
Lost arbitration while transmitting
a data byte as master.
Current SMbus State
Rev. 1.3
No action required (expect-
ing STOP condition).
Load SMB0DAT with next
data byte to transmit.
No action required (expect-
ing Master to end transfer).
Clear STO.
Acknowledge received
address.
Do not acknowledge
received address.
Acknowledge received
address.
Do not acknowledge
received address.
Reschedule failed transfer;
do not acknowledge received
address.
Abort failed transfer.
Reschedule failed transfer.
No action required (transfer
complete/aborted).
Clear STO.
Abort transfer.
Reschedule failed transfer.
Acknowledge received byte;
Read SMB0DAT.
Do not acknowledge
received byte.
Abort failed transfer.
Reschedule failed transfer.
Typical Response Options
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
Written
Values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
1
0
1
0
0
0
1
0
0
0