C8051F34A-GMR Silicon Labs, C8051F34A-GMR Datasheet - Page 185

• Manufacturer Part Number: C8051F34A-GMR
• Description: 8-bit Microcontrollers - MCU 48 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F34A-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
CLRDT
Bit7
W
CLRDT: Clear Data Toggle
Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’.
Read: This bit always reads ‘0’.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. This flag must
be cleared by software.
SDSTL: Send Stall
Software should write ‘1’ to this bit to generate a STALL handshake. Software should write
‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FLUSH: FIFO Flush
Writing a ‘1’ to this bit flushes the next packet to be read from the OUT endpoint FIFO. The
FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets,
software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’
when the FIFO flush is complete.
DATERR: Data Error
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error.
It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
OVRUN: Data Overrun
This bit is set by hardware when an incoming data packet cannot be loaded into the OUT
endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
FIFOFUL: OUT FIFO Full
This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the end-
point (DBIEN = ‘1’), the FIFO is full when the FIFO contains two packets. If DBIEN = ‘0’, the
FIFO is full when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
OPRDY: OUT Packet Ready
Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Soft-
ware should clear this bit after each data packet is unloaded from the OUT endpoint FIFO.
Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should
STSTL
R/W
Bit6
not be used to flush the packet. Instead, the entire data packet should be read from the
FIFO manually.
SDSTL
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
FLUSH
R/W
Bit4
DATERR
Rev. 1.3
Bit3
R
OVRUN
R/W
Bit2
FIFOFUL
Bit1
R
OPRDY
R/W
Bit0
USB Address:
00000000
Reset Value
0x14
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