R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 112

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 4 Resets
4.3.2
RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal
reset signal type. RSTCSR is initialized to H’1F by a pin reset or a deep software standby reset,
but not by the internal reset signal generated by a WDT overflow.
Note:
Rev. 2.00 Sep. 16, 2009 Page 82 of 1036
REJ09B0414-0200
Bit
7
6
5
4 to 0 
Note: * Only 0 can be written to clear the flag.
Bit
Bit name
Initial value:
R/W:
*
Bit
Name
WOVF 0
RSTE

Reset Control/Status Register (RSTCSR)
Only 0 can be written to clear the flag.
R/(W)*
WOVF
7
0
Initial
Value
0
0
1
RSTE
R/W
R/(W)* Watchdog Timer Overflow Flag
R/W
R/W
R
R/W
6
0
Description
This bit is set when TCNT overflows in watchdog timer mode,
but not set in interval timer mode. Only 0 can be written to.
[Setting condition]
When TCNT overflows (H’FF → H’00) in watchdog timer mode.
[Clearing condition]
When this bit is read as 1 and then written by 0.
(The flag must be read after writing of 0, when this bit is cleared
by the CPU using an interrupt.)
Reset Enable
Selects whether or not the LSI internal state is reset by a TCNT
overflow in watchdog timer mode.
0: Internal state is not reset when TCNT overflows. (Although
1: Internal state is reset when TCNT overflows.
Reserved
Although this bit is readable/writable, operation is not affected
by this bit.
Reserved
These are read-only bits but cannot be modified.
R/W
this LSI internal state is not reset, TCNT and TCSR of the
WDT are reset.)

5
0

R
4
1

R
3
1

R
2
1

R
1
1

R
0
1