R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 629
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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15.6.5
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
15.6.6
If the WDTOVF signal is input to the RES pin, this LSI will not be initialized correctly. Make
sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by
means of the WDTOVF signal, use a circuit like that shown in figure 15.6.
15.6.7
When the WDT operates in watchdog timer mode, a transition to software standby mode is not
made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1.
Instead, a transition to sleep mode is made.
To transit to software standby mode, the SLEEP instruction must be executed after halting the
WDT (clearing the TME bit to 0).
When the WDT operates in interval timer mode, a transition to software standby mode is made
through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1.
Internal Reset in Watchdog Timer Mode
System Reset by WDTOVF Signal
Transition to Watchdog Timer Mode or Software Standby Mode
Figure 15.6 Circuit for System Reset by WDTOVF Signal (Example)
Reset signal to entire system
Reset input
Rev. 2.00 Sep. 16, 2009 Page 599 of 1036
Section 15 Watchdog Timer (WDT)
WDTOVF
RES
This LSI
REJ09B0414-0200
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